This application is related to co-assigned applications all of which are incorporated herein by reference:
U.S. patent application Ser. No. 09/154,385 entitled xe2x80x9cMETHOD OF INITIALIZING A CPU CORE FOR EMULATIONxe2x80x9d filed Sep. 16, 1998, now U.S. Pat. No. 6,167,365 granted Dec. 26, 2002; and
U.S. patent application Ser. No. 09/483,367, entitled xe2x80x9cEMULATION SUSPEND MODE WITH DIFFERING RESPONSE TO DIFFERING CLASSES OF INTERRUPTSxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,809 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/481,852, entitled xe2x80x9cEMULATION SUSPENSION MODE WITH STOP MODE EXTENSIONxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,809 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/483,568, entitled xe2x80x9cEMULATION SUSPEND MODE HANDLING MULTIPLE STOPS AND STARTSxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,809 filed Feb. 19, 1999;
U.S. patent application Ser. No. 06/09/483,697, entitled xe2x80x9cEMULATION SUSPEND MODE WITH FRAME CONTROLLED RESOURCE ACCESSxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,809 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/482,902, entitled xe2x80x9cEMULATION SUSPEND MODE WITH INSTRUCTION JAMMINGxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,809 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/483,237, entitled xe2x80x9cEMULATION SYSTEM WITH SEARCH AND IDENTIFICATION OF OPTIONAL EMULATION PERIPHERALSxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,960 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/483,783, entitled xe2x80x9cEMULATION SYSTEM WITH ADDRESS COMPARISON UNIT AND DATA COMPARISON UNIT OWNERSHIP ARBITRATIONxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,791 filed Feb. 19, 1999;
U.S. patent application Ser. No. 09/481,853, entitled xe2x80x9cEMULATION SYSTEM WITH PERIPHERALS RECORDING EMULATION FRAME WHEN STOP GENERATEDxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,810 filed Feb. 19, 1999; and
U.S. patent application Ser. No. 09/483,321, entitled xe2x80x9cEMULATION SYSTEM EMPLOYING SERIAL TEST PORT AND ALTERNATIVE DATA TRANSFER PROTOCOLxe2x80x9d claiming priority from U.S. Provisional Application No. 60/120,667 filed Feb. 19, 1999
The technical field of this invention is complex integrated circuits including embedded digital processor cores and more particularly in circuit emulation of integrated circuits with embedded digital processor cores.
Programmable digital processors such as microprocessors and digital signal processors have become very complex machines. Testing these programmable digital processors has also become complex task. It is now common for semiconductor manufactures to build single integrated circuit programmable digital processors with millions of transistors. The current trend is to devote many of these transistors to on-chip cache memories. Even so, the number of logic circuits and their complex relationships makes testing such integrated circuits an increasingly difficult task.
A trend in electronics makes this testing problem more difficult. Single integrated circuit programmable digital processors are becoming more and more of the electronics of many end products. A single integrated circuit used in this way typically includes a programmable digital processor, read only memory storing the base program, read/write memory for operation and a set of peripherals selected for the particular product. This trend is known as system level integration. In the ultimate system level integration, all the electronics are embodied in a single integrated circuit. This level of integration is now achieved in electronic calculators. Many electronic calculators consist of a single integrated circuit, a keyboard, a display, the battery or solar panel power source and a plastic case. Such integration provides less xe2x80x9cvisibilityxe2x80x9d into the operation of the programmable digital signal processor. Because the address and data busses of the digital processor are no longer brought out the device pins, it is more difficult to determine the behavior of the embedded processor from external connections.
Another trend in electronics makes this testing problem more difficult. Many new product applications require differing types of processing. Often control processes and user interface processes are better handled with a different programmable digital processor than digital signal processes. An example is wireless telephones. Many coding/decoding and filtering tasks are best handled by a digital signal processor (DSP). Other tasks such as dialing, controlling user inputs and outputs are best handled by microprocessors such as a RISC (Reduced Instruction Set Computer) processor. There is a trend for a system integrated circuit to include both a RISC processor and a DSP. These two processors will typically operate independently and employ differing instruction set architectures. Thus there may be more than one programmable digital processor on a single integrated circuit, each having limited visibility via the device pins.
Another problem is product emulation when employing these programmable digital processors. Product development and debugging is best handled with an emulation circuit closely corresponding to the actual integrated circuit to be employed in the final product. In circuit emulation (ICE) is in response to this need. An integrated circuit with ICE includes auxiliary circuit not needed in the operating product included solely to enhance emulation visibility. In the typical system level integration circuit, these emulation circuits use only a very small fraction of the number of transistors employed in operating circuits. Thus it is feasible to include ICE circuits in all integrated circuits manufactured. Since every integrated circuit can be used for emulation, inventory and manufacturing need not differ between a normal product and an emulation enhanced product.
As a result of these trends there is a need in the art for integrated circuits which are easier to test and easier to emulate.
This invention involves in-circuit-emulation of an integrated circuit. The integrated circuit includes a digital data processor capable of executing program instructions. A debug event detector detects predetermined debug event. Upon detection of a debug event, the in-circuit-emulator suspends program execution except for real time interrupts. An emulation monitor program permitting visibility into the state of the integrated circuit is run as such a real time interrupt interrupt.
The integrated circuit includes a serial scan path for control of the state of the integrated circuit, such as a JTAG interface. The in-circuit-emulation selectively assigning emulation resources of the integrated circuit to one of the serial scan path or the monitor program. A monitor privilege input controls this assignment by its digital state. The emulation resource may be a read write data register and the assignment includes accessing the data register.
These and other aspects of this invention are illustrated in the drawings, in which:
FIG. 1 illustrates the environment of the debugging system of this invention which is known in the art;
FIG. 2 illustrates the known 14-pin JTAG header used to interface the target system to the access adapter;
FIG. 3 illustrates an emulation level view of the target system;
FIG. 4 illustrates an electrical connection view of the coupling between the access adapter and the target system; and
FIG. 5 illustrates the possible operation states in the debugging environment of the preferred embodiment of this invention.